1. Field of the Invention
The present invention generally relates to semiconductor memory devices, and more particularly, to a process suitable for testing semiconductor devices having built-in self repair (BISR) memory.
2. Background Information
Integrated circuits have become key components of many consumer and commercial electronic products, often replacing discrete components and enhancing functionality. The semiconductor processing technologies that produce these integrated circuits have advanced to the point where complete systems, including memories, can be reduced to a single integrated circuit or application specific integrated circuit (ASIC) device. It is a common practice for the manufacturers of such integrated circuits to thoroughly test device functionality at the manufacturing site. Because of the increasing complexity of new designs, test development costs can account for a large percentage of the total ASIC development cost.
Before integrated circuits (or “chips”) are released for shipment by a manufacturer, the devices typically undergo a variety of testing procedures. In ASIC devices incorporating integrated memories, for example, specific tests are carried out to verify that each of the memory cells within the integrated memory array(s) is functioning properly. This testing is necessary because perfect yields are difficult to achieve. It is not uncommon for a certain percentage of unpackaged ASIC die to contain memory cells which fail testing processes, due largely to non-systemic manufacturing defects and degradation faults. Such manufacturing issues are likely to increase as process geometries continue to shrink and the density of memory cells increases.
A number of memory testing strategies have evolved. If an embedded memory is buried deeply within an ASIC, a built-in self-test (BIST) is often used by semiconductor vendors. BIST refers in general to any test technique in which test vectors are generated internal to an integrated circuit or ASIC. Test vectors are sequences of signals that are applied to integrated circuitry to determine if the integrated circuitry is performing as designed. BIST can be used to test memories located anywhere on the ASIC without requiring dedicated input/output pins, and can be used to test memory or logic circuitry every time power is applied to the ASIC, thereby allowing an ASIC to be easily tested after it has been incorporated in an end product. Further, since BIST structures remain active on a device, BIST can be employed at the board or system level to yield reduced system testing costs, and to reduce field diagnosis and repair costs. A number of software tools are available for automatically generating BIST circuitry, including RAMBIST Builder by LSI Logic of Milpitas, Calif.
In addition to the aforementioned testing procedures, manufacturers utilize a number of techniques to repair faulty memories when feasible. Such techniques include bypassing faulty cells using laser procedures and fused links that cause address redirection. In order to enhance the repair process, on-chip built-in self repair (BISR) circuitry for repairing faulty memory cells has evolved. BISR circuitry functions internal to the integrated circuit without detailed interaction with external test or repair equipment. In the BISR approach, suitable test algorithms are preferably developed and implemented in BIST or BIST-like circuitry. These test patterns may be capable of detecting stuck-at, stuck-open, and bridging faults during memory column tests, as well as memory cell faults and retention faults during memory tests.
Following execution of the test patterns, the BISR circuitry analyzes the BIST results and, in the event of detected faults, automatically reconfigures the faulty memory utilizing redundant memory elements to replace the faulty ones. A memory incorporating BISR is therefore defect-tolerant. The assignee of the present invention, LSI Logic Corporation, has addressed different methods of repairing faulty memory locations utilizing BIST and BISR circuitry.
While the process of testing and repairing semiconductor memories through BIST and BISR is generally known and practiced in the semiconductor industry, there still exists a need to increase manufacturing yields. In particular, there exists a need for an improved method of testing semiconductor devices, wherein the memories included on such devices are tested under a wide range of operating conditions. Moreover, such testing should be performed both before and after a semiconductor device is assembled into its final packaged form. The present invention addresses these and other issues.